//*****************************************************************************
//
// while.icf
//
// IAR linker Configuration File
//
//*****************************************************************************

//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package.
//
//*****************************************************************************

//
// Define a memory section that covers the entire 4 GB addressable space of the
// processor. (32-bit can address up to 4GB)
//
define memory mem with size = 4G;

//
// Define a region for the flash.
//
define region FLASH = mem:[from 0x0000C000 to 0x000FC000];

//
// Define a region for the SRAM.
//
define region SRAM = mem:[from 0x10010000 to 0x10060000];   // To avoid using TCM for DMA, for demo purpose only
                                                            // Revise this code here in your application!

//
// Define a block for the heap.
//
define block HEAP with alignment = 0x8, size = 0x00010000 { };

//
// Define a block for the stack.
//
define block CSTACK with alignment = 0x8, size = 0x8000 { };

//
// Define a block for the Interrupt Vectors and Patchable Region.
//
define block FLASHBASE with fixed order
{
 readonly section .intvec,
 readonly section .patch
};

//
// Read/Write values should be initialized by copying from flash.
//
initialize by copy { readwrite };

//
// Indicate that the noinit values should be left alone.
//
do not initialize { section .noinit };

//
// Place the interrupt vectors and patchable section at the start of flash.
//
place at start of FLASH { block FLASHBASE };

//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };

//
// Place the stack at the start of SRAM.
//
place at start of SRAM { block CSTACK, section .noinit };

//
// Place all read/write items into SRAM.
//
place in SRAM { block HEAP, readwrite };
