Apollo1 and Apollo2 do not have DMA, which was a conscious decision targeted at providing the lowest power consumption solution possible. Apollo1 and Apollo2 instead rely on large low-power Local RAM/FIFOs for each of the serial interfaces.
For Apollo1, each of the two I2C/SPI masters have 64-byte LRAM/FIFO, the I2C/SPI slave interface has 256-byte LRAM/FIFO, and the UART has 32-byte TX FIFO and 32-Byte RX FIFO. Even the ADC has an 8-sample deep FIFO.
For Apollo2, each of the six I2C/SPI masters have 128-byte LRAM/FIFO, the I2C/SPI slave interface has 256-byte LRAM/FIFO, each of the UARTs have independent 32-byte TX FIFO and 32-byte RX FIFO, and the PDM interface has a 256-word FIFO. Even the ADC has an 16-sample deep FIFO.
These peripherals can operate autonomously with no CPU interaction while there is data/space in the FIFO. The MCU only needs to be involved to load/empty the FIFOs when they reach the configurable threshold levels which trigger an interrupt.
The combination of these FIFOs with the extremely low active power consumption of the MCU core enables nearly all functions to be performed by Apollo at much lower power consumption than other MCUs can achieve using DMA.
Note that DMA capability has been added to Apollo3, partly to support easier code porting from other platforms where DMA was used, as well as to support streaming large amounts of data on the QSPI interface of the Apollo3. However, the deep peripheral FIFOs are retained on Apollo3 so power optimized non-DMA code from Apollo1 and Apollo2 will continue to work on Apollo3.