Why do I sometimes see unexpected faults on the Apollo3 Blue, such as INVSTATE and NOCP, when there is no reason why they should be happening?
The problem is caused by the CPU executing incorrect instruction data instead of the correct data stored in internal Flash. This issue is caused by RAM (one of the cache data RAM sections) not retaining all the correct values during deep sleep. The cached values are correct before going into deep sleep, but some are incorrect immediately after exiting deep sleep upon interrupt, resulting in the fault. This could happen on any revision of the MCU.
Enabling the power-down of the cache in deep sleep mode prevents this issue from happening. The Power Control module's MEMPWRDINSLEEP register write shown below should be done during cache initialization:
PWRCTRL->MEMPWDINSLEEP_b.CACHEPWDSLP = PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN;