Apollo4 Blue / Apollo4 Blue Plus SoC 32 MHz Crystal Calibration

This knowledgebase article describes how to determine whether the 32 MHz crystal needs to be trimmed, and the steps for performing the trim with R4.1.0 and later SDKs.  This KB article is applicable to the Apollo4 Blue SoC (AMA4B2KK-KBR-B2) and Apollo4 Blue Plus SoC (KBR package: AMA4B2KP-KBR; KXR package: AMA4B2KP-KXR).

1. Guidance for determining if trimming of the 32 MHz crystal is needed

The Apollo4 Blue / Blue Plus 32 MHz crystal accuracy requirement is 40 PPM including initial tolerance, temperature drift, and crystal aging.  The crystal must be specified for operation with 6 pF load capacitance and must have an ESR of no more than 100 Ohm.  The initial tolerance of the crystal is the main frequency tolerance in PPM specified for a crystal and specifies how much the crystal may vary from specified frequency when new, at room temp, and with specified load capacitance applied.  The temperature drift will be determined by the crystal specs and is often specified as temperature stability in PPM.  The crystal aging should also be specified by the crystal manufacturer in PPM per year.

For intended operating conditions (temperature) and product lifetime, the total frequency variation should be calculated by adding together the initial tolerance, temperature stability, and aging. This total frequency variance must be less than 40 PPM to guarantee that all BLE will operate reliably across temperature and over the lifetime of the product.  If the calculated total variation exceeds 40 PPM there are two possible solutions:

• Select a crystal with tighter initial tolerance, temperature stability, or aging.
• Perform per-unit calibration trim to reduce the initial tolerance to a much lower PPM which is limited only by production measurement accuracy used to measure the frequency and the Apollo4 Blue / Blue Plus 32 MHz crystal trim step size.

If the crystal tolerance as described above meets the 40 PPM requirement, then a fixed per-design trim may be used. This trim value needs to be determined by measuring the initial frequency on a large population of boards (because the crystals have +/- 20 PPM tolerance) and then calculating the trim for the median frequency. This will center the 20 PPM initial tolerance of this particular board design (crystal+board) at the correct 32 MHz.  

If a crystal with a capacitive load spec other than the recommended 6 pF is used, then the initial frequency of the crystal will be pulled due to being operated with incorrect load capacitance. In this case, crystal trimming will be required. Only use of 6 pF specified crystals is officially supported with Apollo4 Blue.

Note: In all cases, the customer should test and confirm that the initial median frequency and frequency tolerance is correct, with 32 MHz median and < x PPM where "x" is the initial tolerance in PPM used in the calculation to confirm total variance from 32 MHz will be less than 40 PPM.

 2. Instructions for trimming the 32 MHz crystal frequency on the Apollo4 Blue / Apollo4 Blue Plus SoC

1. Download the Apollo4 Blue / Apollo4 Blue Plus example project “uart_ble_bridge”  to the Apollo4 Blue / Apollo4 Blue Plus.
2. Send UART HCI command:  01 1E 20 03 13 25 10 to output a continuous carrier wave of 2440 MHz and measure the frequency accuracy with an appropriate RF instrument.
3. Change the crystal trim:
   • The uart_ble_bridge does not yet have a vendor specific command for trimming the 32 MHz crystal, so this needs to be done by modifying the uart_ble_bridge project. 
   • Use the "am_devices_cooper_crystal_trim_set(void *pHandle, uint32_t ui32TrimValue)" function to set the crystal capacitance trim. 
   • The acceptable trim value is 10 bits, ranging from 0 to 0x3FF (default value = 0x12C).
   • The XTALHSTRIMS register in the MCUCTRL register set contains two trim fields, one for each trim cap:

     • XTALHSCAP2TRIM : 6;  [5..0] xtalhs_cap2_trim

     • XTALHSCAPTRIM : 4;   [9..6] xtalhs_cap_trim

   • The user should set trim values as follows:

     1. SetXTALHSCAPTRIM to a fixed value.

     2. Increase/decrease XTALHSCAP2TRIM to see if the frequency can be trimmed to a good value.

     3. If not, increase/decreaseXTALHSCAPTRIM and repeat steps 1 - 3 until a correct frequency is found.

   • Increase the trims for negative frequency offset, or decrease the trims for positive frequency offset.
4. Remeasure the frequency accuracy and repeat adjusting the trim until the accuracy is within 5 PPM. Test about 20 pieces to get the average trim value to use for all boards.
5. Save the calculated average trim data to a location in the MRAM or INFO0. If using a single value for the project, this can be integrated in the source code.
6. In application code, call the “am_devices_cooper_crystal_trim_set” function at the BLE Init/Bootup process in the application to set the trim value. The “am_devices_cooper_crystal_trim_set” function will set the trim value to bits 0:9 of register XTALHSTRIMS (address 0x40020128).
7. The “am_devices_cooper_crystal_trim_set” function needs to be called prior to calling the "am_devices_cooper_init" function.

//*****************************************************************************
//
// Set the 32M crystal frequency.
//
// ui32TrimValue: default is 0x12C
//
// Refer to KBA "Apollo4 Blue / Apollo4 Blue Plus SoC 32 MHz Crystal Calibration".
//
//*****************************************************************************
uint32_t
am_devices_cooper_crystal_trim_set(void *pHandle, uint32_t ui32TrimValue)
{
    if(ui32TrimValue > 0x3FF)
    {
        return AM_DEVICES_COOPER_STATUS_ERROR;
    }

    //
    // XTALHSCAP2TRIM : 6;  [5..0] xtalhs_cap2_trim
    // XTALHSCAPTRIM : 4;   [9..6] xtalhs_cap_trim
    //

    g_ui32xtalhscap2trim = (ui32TrimValue & MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Msk);
    g_ui32xtalhscaptrim  = (ui32TrimValue & MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Msk) >> MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Pos;  

    return AM_DEVICES_COOPER_STATUS_SUCCESS;
}