General layout guidelines for Apollo MCUs

This articles applies to all existing Apollo MCUs including Apollo1, Apollo2 and Apollo2Blue. 

A good PCB layout has many benefits including but not limited to:

 1) Lower power consumption.

 2) Better signal integrity.

 3) Reduced EMI.

 4) Lower risk of layout related failures.

It is essential for a low-power design to follow these guidelines for a successful layout the first time.

Power and Ground:

1) Power pins like VDDH, VDDA, VCC and VDDP should be connected to power using:

• Power plane (Preferred)
• Power polygon (If power plane is not an option)
• Thick traces (If power plane and power polygon are not options)

2) Decoupling capacitors on the power pins should be as close to the MCU as possible.

3) Ground pins should be connected to the most stable ground sink on the PCB.  It is recommended to have a ground plane or polygon for the connections.

4) Use star topology for connecting ground to the MCU

Buck circuitry: 

Laying out the buck circuit for Apollo MCU is very critical.  Please follow the guidelines below for best results.

1) Inductors and capacitors for the buck circuit should be placed as close to the MCU as possible.

2) Place the buck circuit components on the same layer as the MCU.

3) Minimize the use of vias.

4) Traces for the buck circuit should be as thick as possible.

5) Keep traces for buck circuit as short as possible.

6) The ground should be connected through ground plane or ground polygon.

7) Keep traces to other pins of MCU or unrelated components as far away as possible.

8) Use appropriate PCB stack up according to your design constraints to avoid noise issues.

9) Use a bill of materials similar to the one for EVBs.  BOM for various EVBs can be found in this KB article.

Oscillator circuitry:

1) Oscillator circuit should be placed farther away from the buck circuit.

2) Avoid using vias for the traces from MCU to crystal.

3) Trace capacitance and other factors should be considered when selecting the crystal's loading capacitor.

Example

Image below shows an example design for Apollo2 that follows the above guidelines.

• L1 and L2 are the inductors for buck circuit placed close to Apollo2.
• The traces for L1 and L2 are made as thick as possible.
• C8 and C9 are the capacitors for the buck circuit and are placed as close to the inductors as possible.
• C3 and C5 are decoupling capacitors placed closer to the MCU
• X1, C1 and C2 are placed close to the MCU to avoid longer traces and higher trace capacitance.