Audio codecs are typically run at “audio-friendly” clock frequencies such as 6.144, 12.288, 24.576, and 49.152 MHz. However, the Apollo MCUs' are typically run at 48 MHz clock, which is not audio friendly.

This KB article describes a way to tune the chip's clock to 49.152 MHz (using HFADJ), to achieve exactly 16/48 KHz audio, or to 45.154 MHz to achieve exactly 44.1 KHz audio.

We want to limit the Pulse-Density Modulated clock (PDM CLK) source to 3.25 MHz for digital microphones such as the ST MP34DT04, where the maximum input clock frequency is 3.25 MHz.

48 KHz Audio

To get 48 kHz audio, set the HFXTADJ value to 49,152/32.768 = 1500 (0x5DC).

Run the b0_hfadj example for the applicable EVB from the latest SDK release.

1. Am_hal_clkgen.c

case AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE:

_VAL2FLD(CLKGEN_HFADJ_HFXTADJ, 0x5DC) /* 49.152 MHz */

2. PDM Setting

FS = FPDM_CLKO / (2 x SINC_RATE) = 3072000/(2*32) = 48 KHz

.ui32DecimationRate = 32,
.eClkDivider = AM_HAL_PDM_MCLKDIV_1,
.ePDMClkSpeed = PDM_VCFG_PDMCLKSEL_3MHz //we get 3,072,000 Hz

Figure 1. GPIO7 Clkout: HFRC_DIV16

 

 

 

Figure 2. Measured PDM_CLK, PDMCLKSEL_3MHz

 

 

16 KHz Audio

1. Setting for sysclk is the same as described above.

2. PDM Setting

FS = FPDM_CLKO / (2 x SINC_RATE) = 768000/(2x24)= 16 KHz

.eClkDivider = AM_HAL_PDM_MCLKDIV_1,
.ui32DecimationRate = 24,
.ePDMClkSpeed = AM_HAL_PDM_CLK_750KHZ, //we get 768,000 Hz

 

Figure 3. Measured PDM_CLK, AM_HAL_PDM_CLK_750KHZ

 

 

44.1 KHz Audio

 

1. Setting for sysclk is the same as described above, except adjust the sysclk to 45.1584 MHz.

_VAL2FLD(CLKGEN_HFADJ_HFXTADJ, 0x562) /* 45.1584 MHz */

2. PDM Setting

FS = FPDM_CLKO / (2 x SINC_RATE) = 2822400/(2x32) = 44,100 Hz

.ui32DecimationRate = 32,
.eClkDivider = AM_HAL_PDM_MCLKDIV_1,
.ePDMClkSpeed = PDM_VCFG_PDMCLKSEL_3MHz //we get 2,822,400 Hz

Figure 4. GPIO7 Clkout: HFRC_DIV16

 Figure 5. Measured PDM_CLK, PDM_VCFG_PDMCLKSEL_3MHz

 

 

Attachments provide example (b0_hfadj.7z) and source code(am_hal_clkgen.c).